Fast Power and Energy Efficiency Analysis of FPGA-based Wireless Base-band Processing

Nowadays, demands for high performance keep on increasing in the wireless communication domain. This leads to a consistent rise of the complexity and designing such systems has become a challenging task. In this context, energy efficiency is considered as a key topic, especially for embedded systems in which design space is often very constrained. In this paper, a fast and accurate power estimation approach for FPGA-based hardware systems is applied to a typical wireless communication system. It aims at providing power estimates of complete systems prior to their implementations. This is made possible by using a dedicated library of high-level models that are representative of hardware IPs. Based on high-level simulations, design space exploration is made a lot faster and easier. The definition of a scenario and the monitoring of IP's time-activities facilitate the comparison of several domain-specific systems. The proposed approach and its benefits are demonstrated through a typical use case in the wireless communication domain.Comment: Presented at HIP3ES, 201

Mini-NOVA: A Lightweight ARM-based Virtualization Microkernel Supporting Dynamic Partial Reconfiguration

International audienceToday, ARM is becoming the mainstream family of processors in the high-performance embedded systems domain. In this context, adding a run-time reconfigurable FPGA device to the ARM processor into a single chip makes it possible to combine high performance and flexibility. In this paper, we propose a low-complexity design of system virtualization running on the Zynq platform. Virtualization of software and hardware resources are managed by a custom microkernel. The dedicated features to efficiently manage the dynamic partial reconfiguration (DPR) technology are described in details. The performance of the DPR management is evaluated and presented at the end of this paper

Hardware task context management for fine grained dynamically recon gurable architecture

International audienceToday's FGDRA could now be regarded, not only as prototyping platforms, but also as reliable alternative to ASICs for consumers products production platforms. To deal with such a system, we propose a middleware layer (RTOS) named SMILE, which could manage not only software process but also hardware tasks running on an FGDRA. Preemption issues for hardware tasks on such a system will be treated, introducing the concept of PDR-SoC2. In this paper, our work on hardware FGDRA based task contexts, its management and its evaluation, is exposed

Dynamic Power Evaluation of LTE Wireless Baseband Processing on FPGA

International audienceMobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for FPGA-based systems is presented. It aims at providing accurate and fast power estimations of an entire system prior to its implementation. It also aims at making design space exploration easier. We introduce an innovative scenario-level in order to facilitate the comparison of domain-specific systems. We show the effectiveness of our approach on several LTE baseband configurations which leads to a low absolute error, compared to classic estimations. It also exhibits a high speed-up factor which is determinant during design space exploration. I. INTRODUCTION Today, the data traffic that is generated on mobile networks continues to grow rapidly. According to [1], global mobile data increases of 69% in 2014 and it will have a compound annual growth rate of 57% from 2014 to 2019. To deal with these issues, mobile networks and user equipments tend to constantly adapt their processing capabilities. Among all possible solutions, a popular example is the LTE standard. The complexity of systems like LTE makes their design and development a challenging task, especially when they are implemented in embedded systems in which specific constraints have to be taken into account (power, size, performance , etc.). The number of parameters that can have an impact over power consumption makes the power estimation even more difficult. As the new technologies clearly enhance the performance in terms of throughput, QoS, it also implies a higher power consumption and more heat dissipation. One of the most popular families of digital circuits in embedded systems are the Field Programmable Gate Arrays (FPGA). These devices represent an attractive technology and make it possible to implement complex systems due to their high density of gates and heterogeneous resources. As compare to ASIC that can achieve better performance [2], FPGAs offer more flexibility. FPGA-based systems can be made of IP (Intellectual Property) which are hardware cores that facilitate design reuse and speed up development time. Their power consumption is generally divided into static and dynamic power. Static power comes from leakage currents whereas dynamic power is generated by the transistors switching activity as soon as the circuit is active

Building a RTOS for MPSoC Dataflow Programming

International audienceMultiprocessor Systems-on-Chip (MPSoC) are becoming the standard high performance Digital Signal Processing (DSP) systems. Hardware complexity abstraction is needed to enable efficient MPSoC programming. A major challenge of MPSoC programming is efficiently handling the combination of new features necessary in a MPSoC operating system: load balancing and efficient use of the parallel resources, with the more traditional features of Real-Time Operating Systems (RTOS): resource sharing between applications, task priorities and reactivity to events. This paper presents a method to combine dataflow methods and RTOS features. The resulting system prototypes an RTOS for symmetric multiprocessing MPSoCs whose inputs are dataflow graphs of applications. The prototype is built on the uC/OS-II RTOS. Experimental results are given on a 3GPP Long Term Evolution algorithm executed on a 4-core MPSoC

An ARM-based Microkernel on Reconfigurable Zynq-7000 Platform

The combination of ARM processor and partially reconfigurable FPGA device is an emerging technology in the current embedded domain. In this paper we propose a custom microkernel on a hybrid ARM-FPGA platform, which is capable of managing reconfigurable hardware accelerators. We will introduce the hardware platform on which the microkernel has been developed and focus on the custom architecture supporting the management of partial reconfiguration and software tasks. An actual use case is studied and presented at the end of this paper to demonstrate the feasibility of our approach

Receive Antenna Shift Keying Modulation Testbed for Wireless Communications Systems

International audience—Time Reversal (TR) applied to wireless communications systems has already shown very promising results at low Signal-to-Noise Ratio (SNR). In this paper, we describe a prototype implementing the Receive Antenna Shift Keying (RASK) modulation scheme combined with TR. RASK modulation consists in focusing a signal onto one receive antenna among several antennas. The index of the target receive antenna is updated every symbol duration and is coded by the binary sequence to be transmitted during the considered symbol. For spatial signal focusing, TR pre-filtering technique is used at the transmitter side. In this study, we also propose a very simple and efficient way to discriminate the collected information at the receiver side. This technique allows receivers with low complexity to be implemented in a multiple-input multiple-output (MIMO) configuration. Moreover, we evaluate the performance of RASK modulation according to the number of antennas at the transmitter and receiver side and demonstrate the feasibility of our approach in a realistic scenario

Papaya Plant Regeneration from Adventitious Roots and Virus Coat Protein Gene Transformation (II)

International audienceThis paper describes the first implementation of a custom micro-kernel on a ARM-FPGA platform capable of manag-ing reconfigurable hardware parts dynamically. After de-scribing the structure of the proposed micro-kernel, we will focus on a custom specific system task dealing with the re-configuration management, which is associated to a dedi-cated scheduling mechanism. We will describe the hardware platform on which the microkernel has been ported and pro-vide a use case application in order to demonstrate the fea-sibility of the approach. At the end of this paper, we will provide quantitative results in terms of reconfiguration over-head and microkernel timing performances

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